Learn VHDL or Verilog?

The quick answer is, VHDL, then Verilog.  Yes, both!  There is a lot of existing HDL out there, examples, complete “cores”, etc. and the one you need, or want to look at to get ideas, might be written in the HDL that you decided not to learn.

I learned VHDL first, and I’m working on Verilog here and there.  In my quest of for books, I ended up with one (Digital Design and Computer Architecture, by David and Sarah Harris) that gives the same circuit example in both VHDL and Verilog, on the same page side-by-side, and that really helps.

One thing you notice right away with VHDL is that it is much more verbose.  Personally I like that, since when I’m learning something, trying to remember language nuances can be a headache.  Verilog packs more in to a single statement, and you have to remember that.  VDHL on the other hand, spells things out in great detail. The only example I can think of right off hand is something like this:

See what I mean? I like the technical detail of seeing that my condition consists of the clk signal changing (0 to 1 or 1 to 0) AND that I only care when the clk just went from 0 to 1 (positive edge trigger.) Now that I understand the details, I don’t mind Verilog’s shortcut, but I needed that low level understanding to help solidify things. Then again, I’m one of those people who hates to see programming if() statements written like this:

I don’t like to make assumptions about what is going on, or to remember what the compiler will generate (most likely a “jump if not zero” instruction in this case.)

Here is an example of a Full Adder in both Verilog and VHDL:



Also, when searching around, my perception was that I was finding more examples in VHDL than Verilog.  I have nothing to back that up, other than it just seemed that way.  Almost every example I needed I could find in VHDL.

Ultimately both VHDL and Verilog are describing the same circuit, and you need to make the connection between what you are describing and the actual circuit that comes out of the tools you are using.  Which ever HDL makes the most sense to you, start with that one.  For me it was VHDL.

2 comments to Learn VHDL or Verilog?

  • DG

    I am deciding whether to learn VHDL or Verilog, and this article is definitely nudging me towards Verilog. I am a software guy, and Verilog just looks so much more… to the point. VHDL feels like C++ and Verilog feels like Python.

    Thank you for the comparison.

    • matthew

      Since you mentioned you are a software guy, I would recommend you go with VHDL. Describing circuits (which is what you will be doing with VHDL or Verilog) is not “programming”, and Verilog’s strong similarity to a programming language can get you into trouble. Having to learn an unfamiliar language might help force the disconnect between software and hardware.

      When I started VHDL I too was (still am) a programmer and I managed to get some things working using a programming mind-set, but it only took me to a point. Sooner than later I started getting into situations where circuits were were just not working.

      The break through for me came when I stopped thinking in terms of “software” and started thinking about how I would build the circuit using discrete logic chips (i.e. 74LS series). Once I did that, many many aspects of HDL fell into place and my circuit efficiency (and functionality) went way up.

      Programming is typically a linear set of instructions, hardware is not. When you are working with hardware you have to remember that everything is happening *at the same time*. That is hard for someone with a software background to wrap their head around, and you end up trying to sequence everything in an FSM when all you really needed was some simple combinatorial logic.