Anyone interested in using the F18A in their own computer or microcontroller system, please start with the TMS9918A datasheet since the electrical interface, host CPU interface, and timing specifications of the F18A are the same as the TMS9918A. I’m only going to outline the F18A differences here.
Since the F18A runs at a higher internal clock speed than the 9918A, the “speed limit” or “CPU access window” of the original VDP has been removed for any system with a memory read/write cycle of about 25MHz or less. A 3MHz CPU is not going to over-run the F18A, so let your code rip! 🙂 If you do plan to use an F18A in a system that is clocked over 25MHz, please contact me and I’ll see what I can do.
The F18A does not use any external RAM, so all pins on the original 9918A that were used for DRAM interfacing simply don’t exist on the F18A. There are a few pins that I maintained simply for physical support of the F18A in a 40-pin socket, but six of the twenty-three pins on the F18A are not connected.
The CPUCLK output is optional and can be enabled or disabled via jumper USR4. Some computer systems used the 3.5795MHz output as the main system clock, and on those systems the USR4 jumper needs to be removed (the jumper “on” disables the CPUCLK output and is the default configuration). The Tomy Tutor is one such system that requires the CPUCLK, but only the NTSC version of the system. Any system that originally used a 9928/29 will never need the CPUCLK since the CPUCLK pin was changed to R-Y to support the RGB output.
The GROMCLK signal is always present and defaults to the original 447.44KHz. However, on the F18A the GROMCLK is programmable from 447.44KHz to 195.312KHz. The main reason for this feature is because on the 99/4A computer, the GROMCLK drives the sound chip, and a slower GROMCLK allows for lower audio frequencies. The bottom end of the audio range is 110Hz with the default GROMCLK, but drops to 48Hz with a 195.312KHz GROMCLK. Very significant if you are trying to get some thumping base sounds for a game or similar. The downside is that the internal GROM chips are also clocked by the GROMCLK, and they will also run slower which may affect the speed of GROM-based software like XB. On a non-99/4A system, a programmable frequency output might be handy.
NOTE: The bus to the host CPU (CD0 – CD7) is numbered using TI’s methodology of that time, which was reverse to what the rest of the industry was doing. I maintain the numbering here to remain consistent with the original documentation. Note that this is only a bit “numbering” difference and NOT bit “value” difference. Basically, if you are using a standard 8-bit CPU like a Z80, 6502, or 6809, your data bus would map like this:
F18A – Z80, 6502, 6809, etc.
CD0 <-> D7 MSbit
CD1 <-> D6
CD2 <-> D5
CD3 <-> D4
CD4 <-> D3
CD5 <-> D2
CD6 <-> D1
CD7 <-> D0 LSbit
N/C =|1 U 40|= N/C
N/C =|2 39|= N/C
|3 38|= CPUCLK
|4 37|= GROMCLK
|5 36|= N/C
|6 35|= N/C
|7 34|= #RESET
|8 33|= Vcc
Vss =|12 29|
MODE =|13 28|
#CSW =|14 27|
#CSR =|15 26|
#INT =|16 25|
CD7 =|17 24|= CD0
CD6 =|18 23|= CD1
CD5 =|19 22|= CD2
CD4 =|20 21|= CD3
SIGNATURE PIN I/O DESCRIPTION
=========== === === ==================
CD0 MSB 24 I/O CPU data bus, NOTE the use of "TI numbering"
CD1 23 I/O
CD2 22 I/O
CD3 21 I/O
CD4 20 I/O
CD5 19 I/O
CD6 18 I/O
CD7 LSB 17 I/O
#CSR 15 I CPU-VDP read strobe, active low
#CSW 14 I CPU-VDP write strobe, active low
#INT 16 O CPU interrupt output, active low
MODE 13 I CPU interface mode select, usually the LSb of an address bus
#RESET 34 I Initalizes the VDP, active low (the SYNC of the 9918A is not supported)
CPUCLK 38 O NTSC color burst freq 3.5795MHz, optional via jumper USR4
GROMCLK 37 O Programmable on the F18A from 447.44KHz (default) to 195.312KHz
Vcc 33 I +5v supply
Vss 12 I Ground reference
N/C 1 X Not connected, physical support only
N/C 2 X Not connected, physical support only
N/C 35 X Not connected, physical support only
N/C 36 X Not connected, physical support only
N/C 39 X Not connected, physical support only
N/C 40 X Not connected, physical support only